A major portion of circuitry on integrated circuit chips performing power management is allocated to low drop-out (LDO) regulators. The LDO regulators supply power to both on-chip and off-chip circuitry. The number of LDO circuits on any particular integrated circuit chip can be large, leading to a substantial test time allocated to the testing of LDO circuits. Further, multiple specification measurements of LDO circuits cause an additional load on automatic test equipment (ATE) that affects the time an ATE must be used to test an integrated circuit containing LDO circuitry, comprising device control protocol (DCP), external components and driver software, and adding to test time and product cost.
US 2010/0109435 (Ahmadi et al) is directed to a system, method and apparatus employed to generate multiple, regulated and isolated power supply voltages, wherein a first and second pass transistor are controlled to provide regulated voltage to two separate circuit loads. US 2009/0284246 A1 (Dash et al.) is directed to a device and system for testing a low dropout (LDO) regulator. US 2009/0206919 A1 (Imtiaz), is directed to a circuit and method devoid of trim resistors to optimized output voltage circuit. In US 2009/0072810 A1 (Lee et al) a voltage drop measuring circuit is directed to a sensing circuit and a voltage drop detecting circuit. US 2003/0206025 (Tse et al.) is directed to a switching regulator comprising a power transistor partitioned into a plurality individually addressable transistor segments. In U.S. Pat. No. 7,626,367 B2 (Tsai) an integrated circuit is directed to providing an output voltage substantially equal to a reference voltage using an LDO regulator and include a fast turn-off and fast turn-on circuitry. U.S. Pat. No. 7,459,886 B1 (Potanin et al.) is directed to a circuit and method for simultaneously charging a battery and providing a supply voltage to a load using in part an LDO regulator. U.S. Pat. No. 6,465,994 B1 (Xi) is directed to a low dropout voltage regulator having variable bandwidth depending on load current. U.S. Pat. No. 6,414,537 B1 (Smith) is directed to a voltage regulator circuit with a low dropout voltage and a fast disable capability. In U.S. Pat. No. 6,373,233 B2 (Bakker et al.) a low dropout regulator is directed to a stable condition in the presence of capacitive loads. U.S. Pat. No. 5,929,617 (Brokaw) is directed to an LDO regulator and method for reducing regulator drive when the output voltage of the regulator is going out of regulation caused by a falling input voltage.
A testing method and implementation is needed to reduce the time and cost of testing LDO circuitry on integrated circuit chip comprising the reduction of an ATE to thoroughly test the LDO circuitry to multiple specifications to guarantee proper operation.